1. Field of the Invention
Example embodiments of the present invention relate to methods of manufacturing semiconductor devices. More particularly, example embodiments of the present invention relate to methods of manufacturing semiconductor devices that may include conductive layer patterns.
2. Description of the Related Art
Semiconductor devices may have integrated cells in a chip to increase data transfer rates of the semiconductor devices.
Various attempts may have been pursued to improve the integration of semiconductor devices. As semiconductor devices become more integrated, wirings of the semiconductor devices may be provided as multi-layered structures.
Moreover, as semiconductor devices become more integrated, a distance between the wirings of the semiconductor devices may decrease, and misalignments may occur during a photolithographic process that may be implemented to form a contact hole. The contact hole may expose an insulating interlayer that may be provided between conductive layer patterns. A self-aligned process may have been recently implemented to form the contact hole in an effort to improve the misalignment during the photolithographic process. In the self-aligned process, a spacer may be formed on a sidewall of the conductive layer patterns and then the contact hole may be formed by the photolithographic process.
Although the conventional techniques are generally thought to provide acceptable results, they are not without shortcomings. For example, when a distance between the conductive layer patterns is reduced, a thickness of the spacer formed on a sidewall of the conductive layer pattern (which is called a shoulder margin) may also be reduced. Accordingly, the shoulder margin of the spacer may be decreased as the integration degree of a semiconductor device increases. The spacer may be damaged in the photolithographic process due to the small shoulder margin, and this may cause a breakdown voltage between a contact pad in the contact hole and a bit line to decrease.
If a thickness of the spacer is increased so the shoulder margin of the spacer is sufficiently large, voids may be generated in the portion of the insulation layer existing in a gap space between the bit lines including the spacer.